1. Field of the Invention
The present invention relates to an integrated circuit, more specifically to a computer automated method for designing an integrated circuit, a computer automated system for designing an integrated circuit, and an integrated circuit designed by the computer automated method and system.
2. Description of the Related Art
In manufacturing processes of semiconductor integrated circuits, it has become increasingly important to provide measures to counter random defects caused by adhesion of dust because of miniaturization in recent years. In the layout design process of semiconductor integrated circuits, various measures have been implemented. As the measures in the layout design process, (a) insertion of multiple vias and contacts, (b) spreading wires, (c) increasing wire width, (d) designing a fault tolerant circuit, and the like are effective.
On the other hand, the requirements for miniaturization in recent years have made it difficult to form desired patterns on a wafer even using an accurate mask. To improve design fidelity, technologies called optical proximity correction (OPC) and process proximity correction (PPC) are widely used. The OPC and PPC form a mask pattern to form a pattern on a wafer as designed. Hereinafter, the OPC and PPC are generally referred to as OPC.
Verification of the design fidelity is also important as a measure for systematic defects generated due to each process of the manufacturing process. The systematic defects are generated in a lithography process, an etching process. In a case where a half pitch of design patterns is less than 140 nm, some regions are not sufficiently subjected to the OPC process depending on the design patterns even when a predetermined design rule is followed. The correction by the OPC process is therefore not properly performed, and problems with the wafer shape occur, thus increasing problems reducing the yield (hereinafter, referred to as OPC problems). A measure to correct the OPC problems is a check (hereinafter, referred to as lithography rule check) based on a lithography simulation. In the lithography rule check, the lithography simulation is performed for patterns after OPC. The obtained patterns and the respective design patterns are then compared to detect a portion which could be a device problem. Contents of an error are an error type (open, short, and shortening errors and the like), an error level, and the like. The error level is a fatal error with a problem known (hereinafter, referred to as just a fatal error), the OPC problem (gray zone error) which is not fatal but does not have an enough margin for process variation, or the like.
In small-scale cell design, the lithography rule check in design is performed with these cells arbitrarily arranged. Accordingly, the layout can be modified in advance when the layout includes a pattern where the OPC problem could occur.
On the other hand, in chip or macroblock level design, automatic placement and routing tools and the like are widely used. This can implement a layout dominantly composed of wiring patterns extending in one direction. Accordingly, there are a few variations on the wiring patterns, and the probability of occurrence of the OPC problems is not high.
However, when a design for the yield improvement by the random defect measure, a cross talk measure, and the like fully begin to be carried out in designing chip and macroblock level comparatively large-scale semiconductor integrated circuits, the following problems occur.    (a) Variations of wire patterns increase, and the probability of occurrence of the OPC problems increases.    (b) Because of the increase in the probability of occurrence of the OPC problems, the lithography rule check becomes necessary. The wire patterns occupy a large area, and the lithography rule check requires a large amount of computer resources and processing time. The verification is therefore difficult to perform for a practical period of time.    (c) In the lithography rule check, many gray zone errors are detected. To improve the yield, measures for the gray zone errors are also important. The gray zone errors are detected more than the fatal errors, and measures thereof are complicated. Accordingly, when many errors are detected, it is more difficult to address all the detected errors for the practical period of time.